The levels of integrated circuit integration continue to increase the gap between size, power, and unit cost. For example, in application spaces requiring high performance signal processing for radio communications and similar applications, the three typical implementation options are (1) ASICs (Application Specific Integrated Circuits); (2) DSPs (digital signal processors); and (3) FPGAs (Field Programmable Gate Arrays). For the advantages that each of these alternatives offer, there are disadvantages as well.
ASICs offer high efficiency in speed, unit size, unit cost, and power consumption. The downside of ASICs is the long time to market. This increases exponentially with gate count and speed, and the resulting NRE (Non-Recurring Engineering) cost in low to moderate volume applications. Digital signal processors, on the other hand, have a high degree of programmability. They can even be reprogrammed “on-the-fly,” and their cost is low to moderate, but are highly inefficient because the bulk of their size and substantial power is required for moving data to and from the processing elements, as opposed to actual processing. Field Programmable Gate Arrays can be reprogrammed, but these circuits cannot be programmed “on-the-fly.” Also, the logical gate count ratio ranges from about 10 to 1 to about 100 to 1. Coupled with the special processing requirements of a field programmable gate array, the result is an expensive, high power consuming semiconductor device with a moderate lead-time.
Globally asynchronous, locally synchronous (GALS) circuits can overcome the disadvantages of using highly integrated semiconductor components for wireless communication, digital signal processors and modern ASICs. In a GALS circuit, synchronization of different functional blocks integrated on one semiconductor chip is simplified, which can remedy problems associated with the use of global clocks and the use of deep submicron system-on-a-chip (SOC) designs. Some of these devices use a global time clock for functional blocks (circuit modules) that are embodied in the design. A GALS circuit architecture uses a self-timed communication scheme on typically a coarse grained block level, such that major modules are designed with synchronous clocking. Data exchange can occur between two modules using a full handshake protocol, and each module can run from its own local clock. Asynchronous circuitry that coordinates any clock-driven events with a self-timed operation can be confined to “self-timed wrappers” that are arranged around a clock domain. Thus, a GALS circuit architecture can take advantage of industry-standard synchronous design techniques within an individual clock domain and self-timed operation across clock boundaries.
A GALS circuit architecture typically uses circuit blocks or modules that operate internally synchronously, but communicate with each other asynchronously using a handshake communications protocol. For this reason, with GALS circuits, there is no requirement for individual, locally synchronized circuit blocks to be globally synchronized with each other, as long as individual, locally synchronous blocks follow the required handshake protocol. These blocks can also be combined in many different arrangements, resulting in a high degree of flexibility in the circuit design. Synchronous circuits can be integrated with each other.
Some GALS circuits convert the asynchronous communication between the locally synchronous circuit blocks using an asynchronous wrapping circuit, also referred to as an “asynchronous wrapper.” This structure includes input and output ports and a local clock signal generator. Asynchronous interfaces can be added to locally synchronous (LS) modules and mitigate the clock distribution problems on these large chips, reduce power consumption in the clock distribution, solve problems of clock skew, and simplify reuse of modules because they do not require the same clock signal.
GALS circuits are thus becoming an increasingly popular circuit architecture. Examples of GALS circuits are disclosed in U.S. Patent Publication Nos. 2006/0259529 and 2006/0161797, and WO 2005/088424, the disclosures which are hereby incorporated by reference in their entirety. Many circuit designers, however, desire the size, processing capability and power consumption of an ASIC, but the programmability of a processor with a data flow architecture.